1. Technical Field
The present invention relates to a power semiconductor component produced in the planar technique with a semiconductor body of the one conduction type, in whose surface region adjacent to a main surface there is embedded at least one semiconductor region of another conduction type opposite to the one conduction type.
2. Background Information
Power semiconductor components are characterised by a high electric strength. Examples of such semiconductor components are thyristors or diodes. In order to achieve a high maximum blocking voltage, the design of the edge termination of a semiconductor component is of particular importance. An essential problem of the edge termination lies in controlling the electric field strength in such a way that a premature breakdown is avoided in the case of blocking. In order to achieve this, the equipotential lines in the area of the chip edge have to be led in the case of blocking in a defined manner from the interior of the component to its surface. A further problem of the edge termination is the shielding of the chip edge against electric charges and chemical influences, which can cause local increases in field strength and a reduction in the maximum blocking voltage or parasitic blocking currents. Various designs of edge terminations are described for example in J. Baliga “Modern Power Devices”, John Wiley & Sons, 1987, pages 93–131.
In the case of high-power semiconductor components, which however are not produced in the planar technique, it is known to structure the chip edge by mechanical machining in order to achieve an extension of the space charge region, which reduces the electric surface field. Mechanical machining does not however come into question for power semiconductor components produced in the planar technique, since all the process steps up to the division into individual chips have to take place on the wafer. The etching technique described in DE 34 22 051 A1, for laying open to public inspection the pn-junction, is also eliminated in the case of semiconductor components in the planar technique.
Field-limiting rings, which are also referred to as guard rings, as well as so-called channel stoppers are used to increase the maximum blocking voltage of power semiconductor components.
EP 0 361 318 A2 describes a planar thyristor with several guard rings and a channel stopper. Guard rings and channel stoppers lie within the region of the semiconductor body, which is surrounded by a zone produced by insulation diffusion.
The guard rings can effectively reduce the surface field, but they do not offer any solution against the effect of surface charges, since the low-doped regions lying between the guard rings react very sensitively to freely mobile surface charges and polarisable molecules, and this can lead to an inversion of the surface and thus to a conductive connection between the guard rings. When relatively high voltages are applied and a relatively deep inversion layer is formed, the channel stopper is unable to prevent the formation of a channel and parasitic leakage currents, if the inversion layer extends up to right next to the channel stopper and high field strengths are created there, which can lead to the injection of charge carriers into the space charge region.
A similar function to the guard rings is possessed by so-called “junction termination extensions” (JTE), such as are described for example in U.S. Pat. No. 4,927,772 or DE 195 31 369. But the junction termination extensions also have the same drawbacks as the guard rings.
It is also known to combine the guard rings and JTE structures with so-called magnetoresistors, in order to suppress for the most part the influence of surface charges. These are described for example in U.S. Pat. No. 4,468,686, U.S. Pat. No. 5,714,396, DE 199 33 985 and DE 199 42 679. There is generally deposited over the magnetoresistors a layer of a resistant, adhesive plastic, such as for example polyimide, in order to avoid electrical spark-overs on account of the short distance of the field rings due to space reasons.
DE 100 51 909 A1 describes an edge termination for a power semiconductor component, wherein the location of the curvature and compression of the equipotential lines is placed into a vertically running insulator region. The breakdown field strength of the insulator forming the insulator region has a much higher value than the semiconductor material forming the semiconductor body. This higher breakdown field strength is intended to permit greater curvatures and compressions of the equipotential lines, as a result of which a considerable reduction in the surface requirement can be achieved. A decisive factor is that the semiconductor chip is deeply notched in the edge region. The notch extends virtually over the whole depth of the space charge region, which is formed in the presence of the maximum applied blocking voltage between the semiconductor regions of opposite conduction type. The relatively costly production of the vertical edge termination is a drawback. Moreover, the chip is weakened at the edge, which is a drawback especially during the handling and division of the wafer into individual chips.
Surface structures designed in the manner of a waffle for solar cells are known from U.S. Pat. No. 4,137,123. The waffle-shaped structures are intended to reduce reflections at the solar cells.
The problem underlying the invention is to provide a power semiconductor component capable of being produced relatively simply in the planar technique, with which both the formation of harmful field peaks in the edge termination are avoided and the effect of surface charges is reduced.